Agentic Skill Framework for Analog IC Design

analog-agents

Two AI agents collaborate on your analog front-end — one designs, one verifies. They converge on specs until every schematic is verified.

🎯

Designer

Hand-calc • Netlist • Rationale

⇄

🔬

Verifier

Testbench • Spectre • Margin

View on GitHub See How It Works

Meet the Agents

Two Roles. Clear Boundaries.

Each agent has strict permissions and a defined communication style. No overlap, no ambiguity.

🎯

Designer

Owns the netlist. Thinks in small-signal equations. Shows their math.

Read/write netlist files (.scs, .sp, .net)
Produces rationale.md with design equations
Delivers verified netlist ready for next design stage
Never runs simulations — that's the verifier's job

Communication Style

"Sized M1 20% wider than calc minimum to account for mismatch"

"Increased Cc from 2p to 2.8p to recover 4° phase margin"

🔬

Verifier

Owns the simulation. Never touches the netlist. Always quantifies.

Read-only access to netlist files
Writes testbench, runs Spectre, writes margin-report.md
Reports margin per spec per corner — never just pass/fail
Never modifies the designer's netlist

Communication Style

"phase_margin: measured 41.2°, target ≥45°, short by 3.8° at SS/125°C"

"Increase Cc to ~2.8p; expect −5MHz UGBW tradeoff"

Workflow

Spec In, Silicon Out

A structured convergence loop that mirrors how real analog teams work.

spec.yml

Quantitative targets — gain, bandwidth, phase margin, noise, power. The contract every agent reads.

Designer Agent

Hand-calc sizing, produces Spectre netlist + rationale.md explaining every parameter choice.

Verifier Agent

Read-only netlist access. Writes testbench, runs Spectre, reports margin per spec per corner.

All Specs Pass?

If NO — margin report flows back to designer. Max 3 iterations before escalating to human.

↻ convergence loop (max 3 iterations)

Sign-off Gate

L3 PVT verification mandatory. All specs must pass across all corners with margin.

✓

Verified Schematic

All specs pass across all corners. Verified netlist delivered, ready for the next stage.

Handoff Contracts

Explicit Payloads. No Implicit Assumptions.

Every agent handoff defines what must be delivered and what to expect back.

📋 spec.yml

Quantitative targets + corner definitions

→

🎯 Designer

Returns: netlist.scs + rationale.md

→

🔬 Verifier

Returns: margin-report.md with evidence

→

✓ Converged

All specs pass → verified & delivered

Spec	Measured	Target	Margin	Status
dc_gain	63.4 dB	≥60 dB	+3.4 dB	✓
ugbw	112 MHz	≥100 MHz	+12 MHz	✓
phase_margin	41.2°	≥45°	−3.8°	✗
noise_input	4.2 nV/√Hz	≤5 nV/√Hz	+0.8	✓
power	0.87 mW	≤1.0 mW	+0.13 mW	✓

Staged Verification

Don't Run PVT Until It Works at Typical

Escalate verification deliberately. L1 → L2 → L3.

L1 FUNCTIONAL

Does It Turn On?

Single .op analysis at TT / 27°C / nominal. Check operating point, saturation, bias currents.

TT • 27°C • 1.8V

L2 SPEC

Does It Meet Targets?

AC, noise, transient, DC at typical corner. All spec targets checked with quantified margin.

TT • 27°C • AC + noise + tran + DC

L3 PVT

Does It Survive Corners?

Full corner matrix from spec.yml. Mandatory before sign-off. No shortcuts.

TT • SS • FF • SF • FS × temp × voltage

Central Contract

One Spec Sheet. Every Agent Reads It.

Quantitative, not prose. The spec.yml is not documentation — it is the contract.

spec.yml

block: folded-cascode-ota
process: tsmc28nm
supply: 1.8V

specs:
  dc_gain:      { min: 60, unit: dB }
  ugbw:         { min: 100, unit: MHz }
  phase_margin: { min: 45, unit: deg }
  noise_input: { max: 5,   unit: nV/rtHz }
  power:        { max: 1.0, unit: mW }

corners: # L3 PVT
  - { name: tt_27c,   process: tt, temp: 27 }
  - { name: ss_125c, process: ss, temp: 125 }
  - { name: ff_m40c, process: ff, temp: -40 }

Automation

Hooks That Think For You

Every simulation is auto-checked. Every session starts with context. Every write is guarded.

SessionStart

Context Injection

Injects the analog-agents skill, reads spec.yml summary, checks if virtuoso-bridge is online. The agent knows the project state before you type a word.

PostToolUse

Auto Spec Check

After every Spectre run: parse PSF, compare against spec.yml, append to sim-log.yml, inject margin table into context. Zero manual parsing.

PreToolUse

Permission Guard

Warns when a verifier agent tries to write to .scs/.sp/.net files. The netlist is the designer's territory.

Get Started

Four Steps to Your First Design

Clone the repo git clone https://github.com/Arcadia-1/analog-agents.git

Register the skill ln -s /path/to/analog-agents/skills/analog-agents ~/.claude/skills/analog-agents

Configure servers cp config/servers.example.yml config/servers.yml && vi config/servers.yml

Create spec.yml and invoke Use the analog-agents skill. Design an OTA for spec.yml.